1. Field of the Invention
This invention generally relates to a semiconductor integrated circuit device and a method of manufacturing the same. More particularly, it relates to a technology effectively applicable to a semiconductor integrated circuit device comprising a DRAM (dynamic random access memory).
2. Related Art
DRAMs are typical large capacity semiconductor memories known to date. Recently, as DRAMs are made to have an ever-increasing storage capacity, the area exclusively occupied by the memory cells of a DRAM has to be reduced in order to enhance the degree of integration of the memory cells.
However, the storage capacity of the information storing capacitive elements (hereinafter referred to simply as capacitors) of the memory cells of a DRAM has to be held to a constant level regardless of the DRAM generation by taking the operational margin and software errors as well as other factors of the DRAM into consideration.
Thus, research and development efforts have been paid to improve the structure of capacitors so that a required storage capacity may be secured within a limited area provided exclusively for the capacitors of a DRAM. As a result of such efforts, cubic capacitor structures have been developed by arranging a plate electrode on a lower electrode having a crown-like three-dimensional profile and typically made of polysilicon with a capacitive insulation film interposed between the plate electrode and the lower electrode. Such structures are currently popularly used.
In capacitors having a cubic profile, or cubic capacitors, the capacitor electrode is normally arranged as an upper layer relative to the memory cell selector MISFET (metal insulator semiconductor field effect transistor: hereinafter referred to simply as selector MISFET) so that a large storage capacity may be secured within a relatively small area.
Japanese Patent Application Laid-Open No. 7-122654 describes a cubic capacitor structure known as capacitor over bit line (hereinafter referred to as COB) structure where the capacitor is arranged above the bit line.
In a DRAM having a COB structure, a selector MISFET and a MISFET for the peripheral circuit are formed on a semiconductor substrate and a bit line for writing and reading data and a first wiring layer of the peripheral circuit are formed above the selector MISFET with an interlayer insulation film interposed therebetween. Subsequently, a capacitor is formed by sequentially laying a storage electrode (lower electrode), a capacitive insulation film and a plate electrode (upper electrode) to produce a multilayer structure. The storage electrode of the capacitor is made of polycrystal silicon doped with an n-type impurity substance (phosphor) and connected to one of the semiconductor regions (the source or drain region) of the selector MISFET, which is of the n-channel type. The plate electrode is arranged as an electrode commonly used for a plurality of memory cells and held to a predetermined constant potential.
The bit line is connected to one of the semiconductor regions (source/drain regions) of the selector MISFET through a contact hole cut through the insulation film that covers the selector MISFET. This connection is realized by way of a polycrystal silicon plug formed in the contact hole. The other semiconductor region of the selector MISFET is connected to the capacitor. The bit line is typically made of a low resistance metal material in order to improve the speed of the data writing/reading operation.
In a DRAM having a configuration as described above, tungsten (W) film is used for the bit line or the first wiring layer of the peripheral circuit. The use of tungsten that is more resistive against electro-migration than aluminum (Al) for the bit line or the first wiring layer of the peripheral circuit provides an effective means for securing a prolonged service life for the wires of the DRAM.
However, more often than not, the metal material of the wires and the silicon of the substrate chemically react each other to produce a silicide layer in areas where the wires and the substrate contact each other. The silicide (tungsten silicide) layer formed by the chemical reaction of the tungsten film and the silicon substrate can generate significant stress in the substrate. Therefore, when the bit line or the first wiring layer of the peripheral circuit is made of tungsten film, a metal film has to be formed under the tungsten film so that there may be given rise to a silicide layer that is subjected to little stress by the chemical reaction of the metal film and the silicon substrate.
The above cited patent document describes the use of titanium (Ti) film as metal film that gives rise to a silicide layer with little stress. Titanium film adheres well to insulation film and the titanium silicide (TiSix, xxe2x89xa62) layer it produces as it reacts with the silicon substrate generates little stress in the substrate. Thus, titanium silicide is a material that can advantageously be used for the metal layer to be formed under the tungsten layer.
Additionally, a titanium silicide film formed on the interface between the semiconductor regions (source/drain regions) of the MISFET of the peripheral circuit and the first wiring layer operates as effective means for reducing the contact resistance of the wires of the device.
On the other hand, there is a problem of the chemical reaction between WF6 of the source gas and silicon (Si) that arises when forming a tungsten film by means of a CVD technique. Additionally, the tungsten film can react with silicon in a subsequent heat treatment process if they are held in direct contact with each other. Therefore, for forming a tungsten film on a titanium film by deposition, it is necessary to provide a barrier layer between the two films that adheres well to them in order to prevent any direct contact of WF6 and silicon or tungsten and silicon. The above cited patent document refers to the use of titanium nitride film (TiN) as barrier layer.
DRAMs generally comprises a memory cell array region, a direct peripheral circuit region and an indirect peripheral circuit region. The memory cell array region is a region where selector MISFETs and capacitors are formed, whereas sense amplifiers are formed in the direct peripheral circuit region to detect the presence or absence of a stored electric charge in each capacitor as recorded information. The indirect peripheral circuit region is formed around the direct peripheral circuit region. The word lines and the bit lines in the memory cell array region of a DRAM are processed with minimum processing dimensions in order to provide the DRAM with a maximal degree of integration. Then, in the direct peripheral circuit region, the MISFETs are processed with minimum processing dimensions and arranged at a pitch that is in line with that of arranging the word lines and the bit lines that have been processed with minimum processing dimensions. Furthermore, the gate electrodes and the contact holes for contacting the source/drain regions are generally also processed with minimum processing dimensions. On the other hand, the indirect peripheral circuit region is subjected to less rigorous requirements in terms of device layout and it is less influential in determining the total area of the chip so that the contact holes for contacting the source/drain regions of the MISFETs can be made to have a large bore in order to realize a reliable contact.
However, as the degree of integration is raised for DRAMs, the area in a DRAM exclusively spared for the capacitors is reduced to consequently reduce their storage capacity. Then, it is necessary to improve the sensitivity of the sense amplifiers and provide measures to reduce the capacity of the bit lines so that the presence or absence of a stored electric charge may be reliably detected in each of the capacitors that have only a small capacity. In order to reduce the capacity of the bit lines, it is necessary to reduce the width of the bit lines and increase the gap separating adjacent bit lines or reduce the film thickness of the bit lines so that adjacently located bit lines may face each other with a minimal surface area.
Additionally, it is also necessary to reduce the area occupied by the memory cell array region who is the largest occupier in the DRAM and minimize the surface area of the chip if the degree of integration is to be enhanced for the DRAM. The area occupied by the memory cell array region can be reduced only by optimally selecting the profiles and the positions of the contact holes for contacting the active regions of the selector MISFETs of the memory cells, the word lines, the bit lines and the capacitors as well as other members. Note that the above listed members should not be made to show a complicated profile as a result of such optimization. More specifically, in the memory cell array region, the members are processed for patterning by exploring the technological limits of photolithography because they are processed with minimum processing dimensions. If the members have a complicated profile, defective patterns can be produced by the patterning operation due to interference of rays of light used for exposure as such interference can occur among adjacently located members. Thus, the members are required to show a profile that is as simple as possible. In the case of word lines and bit lines, a linear profile will be the best choice.
However, with bit lines having a linear profile and a minimal width, it will no longer be possible to completely cover the contact area of each bit line and the polycrystal silicon plug formed on the source/drain regions of a corresponding selector MISFET, which is a bit line contact hole, so that consequently and inevitably the bit line contact hole will remain open relative to the bit line. Then, the bit line contact hole will become etched during the operation of etching the bit line.
When bit lines are processed in such an open structure, the polycrystal silicon plug underlying the bit lines can be dug to produce undulations on the underlayer, which adversely affect the subsequent photolithography and etching steps to degrade the overall processing accuracy.
As described earlier, a titanium silicide film is formed between each bit line and the corresponding polycrystal silicon plug to reduce the contact resistance. However, when a bit line is etched in an open structure, the titanium silicide film that is apt to be etched can also be etched transversally to produce a cavity between the bit line and the polycrystal silicon plug. Then, such a cavity can hinder the communication between the bit line and the polycrystal silicon plug to consequently degrade the performance of the DRAM.
On the other hand, as also described earlier, the bit lines and the first wiring layer are formed as a common layer and a titanium silicide film is formed at the contacts of the first wiring layer and the semiconductor substrate. The titanium silicide film has a thermal resistance that is not sufficient to withstand the heat treatment process to be conducted after the formation of the bit lines and the first wiring layer so that a problem of an increased leak current can arise at their contacts. Particularly, the inventors of the present invention have noticed that the thermal resistance is particularly poor when the contact holes have a bore that is different between the direct peripheral circuit region and the indirect peripheral circuit region. Then, such a rise in the leak current, or a fall in the withstand voltage at the contacts, will become particularly remarkable when unreacted titanium is left on the bottom of any of the contact holes.
Thus, it is an object of the present invention to provide a technology for effectively preventing undulations from being produced in the polycrystal silicon plugs in the bit line contact holes to eliminate any possible adverse effect of such undulations on the subsequent photolithography and etching steps and improve the yield of these steps.
Another object of the present invention is to provide a technology for preventing the phenomenon that the silicide film at the contacts of the bit lines and the polycrystal silicon plugs is etched transversally from taking place in order to secure the communication between each bit line and the corresponding polycrystal silicon plug and consequently improve the yield and the reliability of manufacturing semiconductor integrated circuit devices.
Still another object of the present invention is to provide a technology for reducing the capacity of each bit line and hence the storage capacity of a DRAM required to store a given amount of information so that the operating speed of the DRAM may be improved.
A further object of the present invention is to provide a technology for improving the thermal resistance of the contacts between the first wiring layer and the semiconductor substrate and suppressing the leak current at the contacts that can appear in subsequent steps involving the use of heat particularly when the bit lines of the DRAM and the first wiring layer of the peripheral circuit region are formed in a common layer so that consequently the yield and the reliability of manufacturing semiconductor integrated circuit devices may be improved.
These and other objects and the novel features of the present invention will become more apparent by reading the following description made in conjunction with the accompanying drawings.
Some of the different aspects of the present invention will summarily described below.
(1) A semiconductor integrated circuit device according to an aspect of the invention contains a memory cell array region having memory cells including selector MISFETs and capacitors and arranged in array on the principal surface of a semiconductor substrate for a DRAM and a peripheral circuit region including MISFETs and arranged along the periphery of the memory cell array region. More specifically, it comprises polycrystal silicon plugs, each being electrically connected to one of the source/drain regions of a corresponding selector MISFET, bit lines each being connected to the top surface of a corresponding polycrystal silicon plug by way of a first contact hole, and a first wiring layer connected to one of the source/drain regions of each of the MISFETs of the peripheral circuit or the principal surface of the semiconductor substrate by way of second contact holes, wherein a titanium silicide film containing nitrogen or oxygen, a tungsten silicide film containing nitrogen or oxygen, a cobalt silicide film containing nitrogen or oxygen or a cobalt silicide film is formed along the interface of each bit line and the corresponding one of the polycrystal silicon plugs or that of the first wiring layer and one of the source/drain regions of each of the MISFETs of the peripheral circuit or the principal surface of the semiconductor substrate. The impurity contained in the silicide film may be carbon or germanium in place of nitrogen or oxygen.
In a semiconductor integrated circuit device having the above described configuration, a titanium silicide, tungsten silicide or cobalt silicide film containing nitrogen, oxygen, carbon or germanium or a cobalt silicide film containing no impurity is formed along the interface of each bit line and the corresponding one of the polycrystal silicon plugs and therefore, if bit lines shows an open structure, or under a condition where the contact metal of the nitrogen-containing titanium silicide film or the like is exposed to an etching atmosphere, the contact metal operates as etching stopper that prevents the polycrystal silicon plug from being scraped off by etching. As a result, the polycrystal silicon plug would not be dug to produce undulations and any possible adverse effect of such undulations on the subsequent photolithography and etching steps is eliminated to improve the yield of these steps.
Additionally, since the contact metal is not etched, no insufficient communication occurs between the bit lines and the respective polycrystal silicon plugs to further improve the yield of manufacturing such semiconductor integrated circuit devices.
The use of the contact metal as etching stopper is devised by the inventors of the present invention on the basis of their finding that a titanium silicide film and a tungsten silicide film that contain nitrogen, oxygen, carbon or germanium as well as a cobalt silicide film regardless if it that contains or not contains any of the above impurities including nitrogen or the like are resistant against etching.
Thus, a semiconductor integrated circuit device according to the invention and having a configuration as described above shows improved thermal resistance because a titanium silicide, tungsten silicide or cobalt silicide film containing nitrogen, oxygen, carbon or germanium or a cobalt silicide film containing no impurity is formed along the interface of each bit line and the corresponding one of the polycrystal silicon plugs or that of the first wiring layer and one of the source/drain regions of each of the MISFETs of the peripheral circuit or the principal surface of the semiconductor substrate. As a result, a heat treatment step can be conducted after forming the first wiring layer(bit lines) and the leak current in the peripheral circuit region can be reduced to further improve the manufacturing yield. These improved are realized on the basis of a series of experiments conducted by the inventors of the present invention and their finding that the leak current does not increase in a contact hole where a contact metal is formed as a titanium silicide film or the like if it is heat treated in a subsequent step. It may be safe to presume that an increase in the leak current is attributable to coagulation of titanium silicide film or diffusion of titanium atoms into the surrounding impurity diffusing region that takes place as a result of heat treatment and that a titanium silicide film containing nitrogen, oxygen, carbon or germanium successfully suppresses such coagulation or titanium diffusion.
Preferably, the concentration of nitrogen or oxygen is between 1 atomic % and 13 atomic %. The resistance against etching will be reduced if the concentration of nitrogen or oxygen is too low, whereas the contact resistance of the contact metal will be increased to make the latter poorly operative if, on the other hand, the concentration of nitrogen or oxygen is too high. The inventors of the present invention came to find as a result of a series of experiments that there exists an appropriate concentration range for nitrogen or oxygen, which is preferably between latomic % and 13 atomic %. According to the findings of the inventors of the present invention, the impurity is most preferably nitrogen, whose concentration is between 1 atomic % and 3 atomic %.
(2) A semiconductor integrated circuit device according to a second aspect of the invention comprises selector MISFETs arranged in array on the principal surface of a semiconductor substrate, polycrystal silicon plugs, each being formed in a first insulation film on one of the source/drain regions of each of the selector MISFETs, and bit lines formed on a second insulation film arranged on the first insulation film, wherein a first contact hole is formed in the second insulation film on each of the polycrystal silicon plugs and each of the bit lines and the corresponding one of the polycrystal silicon plugs are connected by way of a metal plug formed in the corresponding first contact hole.
In a semiconductor integrated circuit device having the above described configuration, each of the bit lines and the corresponding one of the polycrystal silicon plugs are connected by way of a metal plug formed in the corresponding first contact holes cut through the second insulation film. Thus, if any of the bit lines shows an open structure relative to the corresponding first contact hole, the metal plug operates as etching stopper to prevent the contact metal of the polycrystal silicon plug from being exposed to the etching atmosphere when a patterning operation is conducted for the bit lines. As a result, the polycrystal silicon plug would not be dug to produce undulations and any insufficient communication due to a transversally etched contact metal can be prevented from taking place to consequently improve the yield and the reliability of manufacturing semiconductor integrated circuit devices as in the case of (1) above.
When the first contact hole is filled by a metal plug, the film thickness of the bit line can be made less than a half of the bore of the first contact hole. Such a thin bit line can show a reduced capacity of the bit lines and hence realize a reduced storage capacity of the DRAM or an improved accuracy for detecting the storage capacity.
More specifically, bit lines are arranged very close to the memory cell array of the DRAM and made to show a long profile extending over the memory cell array region between the direct peripheral circuits where sense amplifiers are arranged. Thus, if the bit lines have a large film thickness, adjacently located bit lines may face each other with a large surface area to increase the interline capacitance. An increase in the interline capacitance can reduce the detection sensitivity of the sense amplifiers to consequently degrade the performance of the DRAM. However, according to the invention, since the bit lines are made very thin to minimize the surface area with which adjacently located bit lines face each other and hence the inter-bit-line capacitance can be reduced. As a result, the accuracy of detecting the stored electric charge in each capacitor can be improved. Additionally, since the response speed of a capacitor is inversely proportional to the product of the stray capacitance and the resistance, the decrease in the interline capacitance can improve the response speed.
Still additionally, the bit lines and the metal plugs may respectively be made of tungsten or molybdenum and titanium nitride or tungsten nitride. Then, the bit lines may be appropriately etched by means of a fluorine type etching gas, whereas the metal plugs made of titanium nitride or tungsten nitride will hardly be etched by the fluorine type etching gas during the bit line patterning operation because of the low etching rate of such an etching gas. Therefore, the bit line patterning operation affords a sufficient degree of over-etching to allow a wide process margin.
In short, in a semiconductor integrated circuit device according to (1) or (2) above, the bit lines are made of a material that can be selectively etched relative to the underlying material in the first contact holes. The underlying material in the first contact holes is selected from materials that have a high etching-resistivity if compared with the bit lines and include nitrogen-containing titanium silicide or the like and titanium nitride or the like that is used for the metal plugs. By selecting an appropriate material having a high etching resistivity relative to the bit lines for the underlayer, undulations due to uniformly scraped underlying polycrystal silicon plugs and defective communication due to transversally etched contact metal can be prevented from occurring if the bit lines show an open structure as described above.
The metal plugs may be made of a laminate having a titanium nitride layer and a tungsten layer, while the bit liens may be of a single layer structure of tungsten. If such is the case, the etching selectivity of the single tungsten layer of the bit lines may not be able to be defined relative to the underlayer because the metal plugs, or the underlayer of the first contact holes, contain tungsten. However, the tungsten film of the bit lines can be made very thin and, if it is over-etched, the over-etching time may represent only about 50% of the film thickness of the bit lines, while the tungsten of the underlayer, or the metal plugs, will be etched only slightly during this time. In short, if bit lines are made of the material of the metal plugs, the plugs will not be etched down to the bottom by over-etching and hence the silicide film at the bottom of the plugs may be free from any trouble such as an etched side.
(3) A semiconductor integrated circuit device according to a third aspect of the invention comprises selector MISFETs arranged in array on the principal surface of a semiconductor substrate, polycrystal silicon plugs, each being formed in a first insulation film on one of the source/drain regions of each of the selector MISFETs, a second insulation film formed on the first insulation film by deposition and bit lines, each being connected to a corresponding one of the polycrystal silicon plugs by way of a first contact hole bored through the second insulation film on the polycrystal silicon plugs, wherein thickness L1 of the bit lines, distance L2 obtained by adding the thickness of the second insulation film and the thickness L1 of the bit lines and bore D of the first contact holes show a relationship of L1xc3x97(1+OVE) less than L2 and L1 greater than D/2 (where OVE is the extent of over-etching of the bit lines in the patterning process).
With a semiconductor integrated circuit device defined as above, where the requirement of L1 greater than D/2 is satisfied and the first contact holes are completely filled with a coating film that eventually makes bit lines, while the requirement of L1xc3x97(1+OVE) less than L2 is met to make the thickness of the bit lines in the first contact holes that is approximated by distance L2 obtained by adding the thickness of the second insulation film and the thickness L1 of the bit lines exceed the extent of etching as expressed by L1xc3x97(1+OVE), the coating film is left, if partly, in the first contact holes when the patterning operation for producing the bit lines is over. Under such a condition where the coating film still exists, the contact metal and the polycrystal silicon plugs will never be etched so that the above identified problems of undulations and defective communication will not occur. Therefore, as pointed out above under (1) and (2), a wide process margin will be allowed to consequently improve the yield and the reliability of manufacturing semiconductor integrated circuit devices.
Note that, in a semiconductor integrated circuit device according to any of (1) through (3) above, the bit lines may have a width smaller than the bore of the first contact holes so that the bit lines may show an open structure relative to the respectively contact holes. While an open structure as used herein refers to a structure that is intentionally made open in the stage of designing the mask, it may be needless to say that the present invention also applies well to a situation where an open structure is unintentionally produced as a result of a displaced mask during the manufacturing process.
(4) A semiconductor integrated circuit device according to a fourth aspect of the invention contains a memory cell array region having memory cells including selector MISFETs and capacitors and arranged in array on the principal surface of a semiconductor substrate for a DRAM, a direct peripheral circuit region formed along the periphery of the memory cell array region and an indirect peripheral circuit region arranged along the periphery of the memory cell array region and comprises contact holes connecting the principal surface of the semiconductor substrate in the direct peripheral circuit region or the indirect peripheral circuit region and the first wiring layer, wherein the bore of the contact holes is identical both in the direct peripheral circuit region and in the indirect peripheral circuit region.
With a semiconductor integrated circuit device having a configuration as described above, where the bore of the contact holes is identical both in the direct peripheral circuit region and in the indirect peripheral circuit region, the thermal resistance of the contact areas of the first wiring layer and the semiconductor substrate is raised to reduce the contact resistance and hence the leak current of the semiconductor integrated circuit device as a whole to consequently improve the yield and the reliability of manufacturing semiconductor integrated circuit devices as well as the performance of the devices.
More specifically, as a result of the fact that the bore of the contact holes is identical throughout the device, each of the layers including a titanium layer, a titanium nitride layer and a tungsten layer for forming wires and arranged in the contact holes to cover the bottom thereof shows a uniform thickness at the bottom in all the contact holes. As each of the layers has a uniform thickness on the bottom in all the contact holes, its thermal resistance does not vary among the contact holes to consequently improve the thermal resistance of the wires arranged in the bottom of each of the contact holes. Particularly, when the titanium layer is made to show a uniform thickness on the bottom in all the contact holes, a uniform titanium silicide film may be produced so that no unreacted titanium film may be left after the silicifying reaction. If, to the contrary, unreacted titanium film is left after the silicifying reaction, the unreacted titanium may be silicified in a subsequent heat treatment process to give rise to unexpected stress in the titanium silicide film and/or produce voids in the semiconductor substrate, which can eventually reduce the thermal resistance of the device. However, the a semiconductor integrated circuit device according to the invention is free from such a problem.
The inventors of the present invention found as a result of a series of experiments that an uneven film thickness of the titanium film in the contact holes can give rise to a residual titanium film left after the silicifying reaction, which by turn reduces the thermal resistance of the device as a whole.
The aspect ratio of the contact holes may be made identical throughout the memory cell array region, the direct peripheral circuit region and the indirect peripheral circuit region. If the bore of the contact holes varies in the device, the film thickness at the bottom of the contact holes can be made uniform in the entire device if the aspect ratio is made identical in the device. Thus, any degradation in the thermal resistance of the device due to a varying film thickness of the titanium film can be prevented from taking place.
(5) A method of manufacturing a semiconductor integrated circuit device according to a fifth aspect of the invention comprises steps of (a) arranging selector MISFETs in array in a memory cell array region, forming MISFETs for peripheral circuits in a peripheral circuit region and forming a first insulation film by deposition to cover the selector MISFETs and the MISFETs for the peripheral circuits, (b) forming first contact holes in the first insulation film, each being provided to expose at least one of the source/drain regions of a corresponding selector MISFET, and forming a polycrystal silicon plug in each of the first contact holes, (c) forming a second insulation film on the first insulation film and the polycrystal silicon plugs by deposition and forming second contact holes in the second insulation film to expose the top surface of the polycrystal silicon plugs, (d) forming third contact holes to expose the source/drain regions of the MISFETs of the peripheral circuits or the principal surface of the semiconductor substrate and (e) forming an electro-conductive film on the second insulation film by deposition and forming bit lines in the memory cell array region and wires of a first wiring layer in the peripheral circuit region by patterning the electro-conductive film, wherein an additional step of forming a member showing an etching rate lower than that of the electro-conductive film of the etching technique for patterning the electro-conductive film in the inside or the bottom of each of the second or the third contact holes is provided prior to the step (e).
With such a method of manufacturing a semiconductor integrated circuit device, an additional step of forming a member showing an etching rate lower than that of the electro-conductive film of the etching technique for patterning the electro-conductive film in the inside or the bottom of each of the second or third contact holes is provided prior to the step (e) so that the member can be used as etching stopper when etching the electro-conductive film for a patterning operation for producing bit lines. Thus, the polycrystal silicon plugs or the contact metal, if such is formed on the upper surface of each of the polycrystal silicon plugs, would not be etched at all. As a result, the polycrystal silicon plugs would not be dug nor the contact metal would be transversally etched so that the device will be free from undulations and bit lines that are defective for communication.
The members can be used as etching stopper for the etching operation of forming bit lines in the step (e) so that bit lines can be made to show a width smaller than the bore of the second contact holes. In other words, the bit lines can be made to show an open structure relative to the respective second contact holes to adapt the semiconductor integrated circuit device to a higher degree of integration and a reduction in the capacity of the bit lines.
The members can be prepared as silicide film produced by thermally treating the cobalt, titanium or tungsten film formed on the second insulation film and containing nitrogen, oxygen, carbon or germanium to a concentration level between 1 atomic % to 13 atomic % and causing a silicifying reaction to take place between the film and the polycrystal silicon plugs or the principal surface of the semiconductor substrate. The silicide film prepared in an above described manner contains nitrogen, oxygen, carbon or germanium to a concentration level between 1 atomic % to 13 atomic % and hence shows a resistivity against etching as pointed out earlier. If the film contains nitrogen, the resistivity of the film against etching can be made remarkably by limiting the nitrogen concentration between 1 atomic % and 3 atomic %.
The members may be plugs made of tungsten, titanium nitride or tungsten nitride and formed in the second or third contact holes respectively. Then, the plugs formed in the contact holes operate as etching stoppers.
With a manufacturing method as described above, the third contact holes arranged for the peripheral circuits may be made to show a same and identical bore. Then, the thermal resistance of the contact areas of the first wiring layer and the semiconductor substrate at the bottom of the third contact holes will be improved.
(6) In a semiconductor integrated circuit device according to the invention, the titanium, tungsten or cobalt silicide film is made to have a film thickness between 15 and 30 nm. As a result of a series of experiments, the inventors of the present invention found that, with a film thickness between 15 nm and 30 nm selected for the silicide film, the contact resistance of the device can be remarkably reduced in the film.
The present invention will be summarized below for all the aspects thereof.
1. A semiconductor integrated circuit device having first MISFETs for selecting memory cells formed on the principal surface of a semiconductor substrate and second MISFETs for peripheral circuits formed on the surface, comprising: polycrystal silicon plugs formed in a first insulation film and arranged on one of the source/drain regions of each of the first MISFETs; bit lines arranged on a second insulation film and electrically connected to the respective polycrystal silicon plugs by way of respective contact holes formed to pass through the second insulation film arranged on the first insulation film; and wires of a first wiring layer arranged on the second insulation film and electrically connected to the source/drain regions of the second MISFETs respectively by way of second contact holes formed to pass through the first and second insulation films; wherein a silicide film of an element selected from titanium, tungsten and cobalt containing an impurity or impurities, or a cobalt silicide film containing no impurity is formed in the contact areas of the bit lines and the polycrystal silicon plugs, or in those of the wires of the first wiring layer and the source/drain regions or the gate electrodes of the second MISFETs or the principal surface of the semiconductor substrate; the impurity or impurities being one or more than one elements selected from nitrogen, oxygen, carbon and germanium.
2. A semiconductor integrated circuit device according to claim 1, wherein a concentration of the impurity is between 1 atomic % and 13 atomic %.
3. A semiconductor integrated circuit device according to claim 2, wherein the impurity is nitrogen, and the concentration of nitrogen is between 1 atomic % and 3 atomic %.
4. A semiconductor integrated circuit device according to claim 1, wherein the width of the bit lines is not greater than the bore of the first contact holes.
5. A semiconductor integrated circuit device comprising: first MISFETs for selecting memory cells formed on the principal surface of a semiconductor substrate; polycrystal silicon plugs formed in a first insulation film and arranged on one of the source/drain regions of each of the first MISFETs; and bit lines arranged on a second insulation film on the first insulation film; wherein first contact holes are formed to pass through the second insulation film; and the bit lines and the polycrystal silicon plugs are connected respectively by way of first plugs formed in the respective first contact holes.
6. A semiconductor integrated circuit device according to claim 5, wherein the surface of the first insulation film and that of the second insulation film are planarized at least in a region where the first MISFETs are formed; and the surface of the first plugs and that of the second insulation film are located on a same plane.
7. A semiconductor integrated circuit device according to claim 5, wherein the film thickness of the bit lines is not greater than a half of the bore of the first contact holes.
8. A semiconductor integrated circuit device according to claim 5, wherein the width of the bit lines is not greater than the bore of the first contact holes.
9. A semiconductor integrated circuit device according to claim 5, wherein the bit lines are made of a material that can be selectively etched relative to the first plugs.
10. A semiconductor integrated circuit device according to claim 5, wherein the bit lines are made of a single layer film of tungsten or molybdenum; and the first plugs are made of a laminate film having a titanium nitride layer and a tungsten layer, or of titanium nitride or of tungsten nitride film.
11. A semiconductor integrated circuit device according to claim 5, wherein it further comprises second MISFETs for peripheral circuits formed on the principal surface of a semiconductor substrate and wires of a first wiring layer arranged on the second insulation film; second contact holes being formed to pass through the first and second insulation films; the wires of the first wiring layer and the source/drain regions or the gate electrodes of the second MISFETs or the principal surface of the semiconductor substrate being electrically connected by way of second plugs formed respectively in the second contact holes; the first and second plugs being made of a same material; and the first wiring layer and the bit lines being made of a same material.
12. A semiconductor integrated circuit device according to claim 11, wherein the surface of the first insulation film and that of the second insulation film are planarized over the entire surface of the semiconductor substrate; and the surface of the first plugs and that of the second insulation film are located on a same plane.
13. A semiconductor integrated circuit device according to claim 11, wherein the bit lines and the first wiring layer are made of a single layer film of tungsten or molybdenum; and the first and second plugs are made of a laminate film having a titanium nitride layer and a tungsten layer, or of titanium nitride or of tungsten nitride.
14. A semiconductor integrated circuit device according to claim 11, wherein a silicide film of an element selected from titanium, tungsten and cobalt containing an impurity or impurities, or a cobalt silicide film containing no impurity is formed in the contact areas of the first plugs and the polycrystal silicon plugs or in those of the second plugs and the source/drain regions or the gate electrodes of the second MISFETs or the principal surface of the semiconductor substrate; the impurity or impurities being one or more than one elements selected from nitrogen, oxygen, carbon and germanium; and a concentration of the impurity or impurities being between 1 atomic % and 13 atomic %.
15. A semiconductor integrated circuit device according to claim 14, wherein the impurity is nitrogen, and the concentration of nitrogen being between 1 atomic % and 3 atomic %.
16. A semiconductor integrated circuit device according to claim 11, wherein a silicide film of an element selected from titanium, tungsten and cobalt is formed in the contact areas of the first plugs and the polycrystal silicon plugs, or in those of the second plugs and the source/drain regions or the gate electrodes of the second MISFETs or the principal surface of the semiconductor substrate, or in the surface areas of the sources/drains of the second MISFETs; and the film thickness of the silicide film in any of the contact areas and the surface areas is between 15 and 30 nm.
17. A semiconductor integrated circuit device according to claim 16, wherein the second MISFETs include p-channel type MISFETs; and the film thickness of the silicide film formed on the surface areas of the sources/drains of the p-channel type MISFETs or in the contact areas of the bottoms of the second plugs and the source/drain regions of the p-channel type MISFETs is between 15 and 30 nm.
18. A semiconductor integrated circuit device comprising: first MISFETs for selecting memory cells arranged on the principal surface of a semiconductor substrate; polycrystal silicon plugs formed in a first insulation film and arranged on one of the source/drain regions of each of the first MISFETs; a second insulation film formed on the first insulation film; and bit lines connected to the respective polycrystal silicon plugs by way of respective first contact holes formed to pass through the second insulation film; wherein thickness L1 of the bit lines, distance L2 obtained by adding the thickness of the second insulation film and the thickness L1 of the bit lines, and bore D of the first contact holes show a relationship of L1xc3x97(1+OVE) less than L2 and L1 greater than D/2 (where OVE is the extent of overetching of the bit lines in the patterning process).
19. A semiconductor integrated circuit device according to claim 18, wherein the width of the bit lines is not greater than the bore of the first contact holes.
20. A semiconductor integrated circuit device containing: a memory cell region having first MISFETs for selecting memory cells arranged in array on a principal surface of a semiconductor substrate; a direct peripheral circuit region formed along the periphery of the memory cell region; an indirect peripheral circuit region arranged along the periphery of the direct peripheral circuit region; and contact hole formed in an insulating film over the principal surface of the direct or indirect peripheral circuit region; wherein the bore of the contact holes is identical both in the direct peripheral circuit region and in the indirect peripheral circuit region.
21. A semiconductor integrated circuit device according to claim 20, wherein the aspect ratio of the contact holes is identical throughout the memory cell region, the direct peripheral circuit region and the indirect peripheral circuit region.
22. A semiconductor integrated circuit device having first MISFETs for selecting memory cells formed on the principal surface of a semiconductor substrate and second MISFETs for peripheral circuits formed on the surface, comprising: polycrystal silicon plugs formed in a first insulation film and arranged on one of the source/drain regions of each of the first MISFETs; bit lines arranged on a second insulation film and electrically connected to the respective polycrystal silicon plugs by way of respective contact holes formed to pass through the second insulation film arranged on the first insulation film; and wires of a first wiring layer arranged on the second insulation film and electrically connected to the source/drain regions of the second MISFETs respectively by way of second contact holes formed to pass through the first and second insulation films; wherein a silicide film of an element selected from titanium, tungsten and cobalt is formed in the contact areas of the first plugs and the polycrystal silicon plugs, or in those of the second plugs and the source/drain regions or the gate electrodes of the second MISFETs or the principal surface of the semiconductor substrate, or in the surface areas of the sources/drains of the second MISFETs; and the film thickness of the silicide film in any of the contact areas and the surface areas is between 15 and 30 nm.
23. A semiconductor integrated circuit device according to claim 22, wherein the second MISFETs include p-channel type MISFETs; and the film thickness of the silicide film formed on the surface areas of the sources/drains of the p-channel type MISFETs or in the contact areas of the wires of the first wiring layer and the source/drain regions of the p-channel type MISFETs is between 15 and 30 nm.
24. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming first MISFETs for selecting memory cells and a first insulation film for covering the first MISFETs, and etching the first insulation film in order to have openings on at least one of the source/drain regions of each of the first MISFETs; (b) depositing a polycrystal silicon film on the surface of the semiconductor substrate to fill the openings of the first insulation film and forming polycrystal silicon plugs electrically connected to the source/drain regions of the first MISFETs by removing the polycrystal silicon film on the first insulation film; (c) forming a second insulation film on the first insulation film and then forming first contact holes in the second insulation film by etching the second insulation film in order to expose the surface of polycrystal silicon plugs; (d) depositing a metal film containing titanium, tungsten or cobalt as principal ingredient and one or more than one impurities selected from nitrogen, oxygen, carbon and germanium, or a cobalt film containing no impurity on the bottom of the first contact holes and on the second insulation film, and then heat-treating the metal film; (e) depositing a first electro-conductive film on the metal film or the cobalt film, whichever appropriate, to fill the first contact holes; and (f) forming bit lines by etching the first electro-conductive film and the metal film or the cobalt film.
25. A method of manufacturing a semiconductor integrated circuit device according to claim 24, wherein the silicide film formed by the heat treatment in the contact areas of the metal film or the cobalt film, whichever appropriate, operates as etching stopper in the subsequent etching step.
26. A method of manufacturing a semiconductor integrated circuit device according to claim 24, wherein the pattern width of each bit lines is not greater than the bore of the first contact holes.
27. A method of manufacturing a semiconductor integrated circuit device according to claim 24, wherein the impurity concentration of the metal film is between 1 atomic % and 13 atomic %.
28. A method of manufacturing a semiconductor integrated circuit device according to claim 27, wherein the impurity is nitrogen and the nitrogen concentration of the metal film is between 1 atomic % and 3 atomic %.
29. A method of manufacturing a semiconductor integrated circuit device according to claim 24, wherein the first electro-conductive film is a laminate film having a titanium nitride layer and a tungsten layer.
30. A method of manufacturing a semiconductor integrated circuit device according to claim 24, wherein second MISFETs for peripheral circuits are formed in the step of forming the first MISFETs; second contact holes for electrically connecting to the source/drain regions or the gate electrodes of the second MISFETs or the principal surface of the semiconductor substrate are formed in the step of forming the first contact holes or immediately before or after the step of forming the first contact holes; a first wiring layer for peripheral circuits is formed in the step of forming the bit lines.
31. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming first MISFETs for selecting memory cells and a first insulation film for covering the first MISFETS, and etching the first insulation film in order to have openings on at least one of the source/drain regions of each of the first MISFETs; (b) depositing a polycrystal silicon film on the surface of the semiconductor substrate to fill the openings of the first insulation film and forming polycrystal silicon plugs electrically connected to the source/drain regions of the first MISFETs by removing the polycrystal silicon film on the first insulation film; (c) forming a second insulation film on the first insulation film and then forming first contact holes in the second insulation film by etching the second insulation film in order to expose the surface of polycrystal silicon plugs; (d) depositing a first electroconductive film to fill the first contact holes and forming first plugs made of the first electro-conductive film in the first contact holes by removing the first electro-conductive film on the second insulation film; (e) depositing a second electro-conductive film on the first plugs and the second insulation film; and (f) patterning the second electroconductive film to produce bit lines.
32. A method of manufacturing a semiconductor integrated circuit device according to claim 31, wherein the first insulation film is planarized by means of a CMP technique before the step of etching the first insulation film; and the first plugs are formed by polishing the first electro-conductive film by means of a CMP technique.
33. A method of manufacturing a semiconductor integrated circuit device according to claim 31, wherein the film thickness of the second electro-conductive film is not greater than the bore of the first contact holes.
34. A method of manufacturing a semiconductor integrated circuit device according to claim 31, wherein the width of the bit lines is not greater than the bore of the first contact holes.
35. A method of manufacturing a semiconductor integrated circuit device according to claim 31, wherein the second electro-conductive film is made of a material having an etching selectivity relative to the first plugs.
36. A method of manufacturing a semiconductor integrated circuit device according to claim 31, wherein the first electro-conductive film is a laminate film including a titanium nitride film and a tungsten film or a single layer film of titanium nitride or tungsten nitride; and the second electro-conductive film is a single layer film of tungsten or molybdenum.
37. A method of manufacturing a semiconductor integrated circuit device according to claim 31, wherein second MISFETs are formed for peripheral circuits in the step of forming the first MISFETs; and second contact holes for electrically connecting to the source/drain regions of the second MISFETs are formed in the step of forming the first contact holes or immediately before or after the step of forming the first contact holes; second plugs made of the first electro-conductive film are formed in the second contact holes in the step of forming the first plugs; and a first wiring layer made of the second electro-conductive film is formed for peripheral circuits in the step of forming the bit lines.
38. A method of manufacturing a semiconductor integrated circuit device according to claim 37, wherein it further comprises; a step of depositing a metal film containing titanium, tungsten or cobalt as principal ingredient and one or more than one impurities selected from nitrogen, oxygen, carbon and germanium to a concentration between 1 atomic % and 13 atomic % or a cobalt film containing no impurity on the bottom of the first and second contact holes and on the second insulation film, and then heat-treating the metal film before forming the first and second plugs.
39. A method of manufacturing a semiconductor integrated circuit device according to claim 37, wherein it further comprises: a step of depositing a metal film containing titanium, tungsten or cobalt as principal ingredient to a film thickness between 10 and 20 nm on the bottom of the first and second contact holes and on the second insulation film, and then heat-treating the metal film before forming the first and second plugs.
40. A method of manufacturing a semiconductor integrated circuit device according to claim 37, wherein it further comprises: a step of depositing a film of silicide of titanium, tungsten or cobalt to a film thickness between 15 and 30 nm on the bottom of the first and second contact holes and on the second insulation film, and then heat-treating the metal film before forming the first and second plugs.
41. A method of manufacturing a semiconductor integrated circuit device according to claim 37, wherein it further comprises: a step of depositing a metal film containing titanium, tungsten or cobalt as principal ingredient and then a silicon film having a film thickness smaller than that of the metal film on the bottom of the first and second contact holes and on the second insulation film, and then heat-treating the metal film before forming the first and second plugs.
42. A method of manufacturing a semiconductor integrated circuit device according to claim 37, wherein it further comprises: a step of depositing a metal film containing titanium, tungsten or cobalt as principal ingredient on the bottom of the first and second contact holes and on the second insulation film, and annealing the metal film in an atmosphere of silicon hydride gas before forming the first and second plugs.
43. A method of manufacturing a semiconductor integrated circuit device according to claim 39, wherein the unreacted titanium, tungsten or cobalt is selectively removed by etching after the step of heat-treating the metal film.
44. A method of manufacturing a semiconductor integrated circuit device according to claim 40, wherein the unreacted titanium, tungsten or cobalt is selectively removed by etching after the step of heat-treating the metal film.
45. A method of manufacturing a semiconductor integrated circuit device according to claim 41, wherein the unreacted titanium, tungsten or cobalt is selectively removed by etching after the step of heat-treating the metal film.
46. A method of manufacturing a semiconductor integrated circuit device according to claim 42, wherein the unreacted titanium, tungsten or cobalt is selectively removed by etching after the step of heat-treating the metal film.
47. A method of manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming MISFETs on the principal surface of a semiconductor substrate and then an insulation film for covering the MISFETs; (b) etching the insulation film in order to have openings on the source/drain regions of the MISFETs; (c) depositing an electro-conductive film to fill the openings, forming wires; and (d) depositing a metal film containing titanium, tungsten or cobalt as principal ingredient to a film thickness between 10 and 20 nm on the bottom of the contact holes and on the insulation film prior to forming said electro-conductive film, and heat-treating it.
48. A method of manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming MISFETs on the principal surface of a semiconductor substrate and then an insulation film for covering the MISFETs; (b) etching the insulation film in order to have openings on the source/drain regions of the MISFETs; (c) depositing an electro-conductive film to fill the openings, forming wires; and (d) depositing a film of silicide of titanium, tungsten or cobalt to a film thickness between 15 and 30 nm on the bottom of the contact holes and on the insulation film prior to forming said electro-conductive film.
49. A method of manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming MISFETs on the principal surface of a semiconductor substrate and then an insulation film for covering the MISFETs; (b) etching the insulation film in order to have openings on the source/drain regions of the MISFETs; (c) depositing an electro-conductive film to fill the openings, forming wires; and (d) depositing a metal film containing titanium, tungsten or cobalt as principal ingredient and then a silicon film having a film thickness smaller than that of the metal film on the bottom of the contact holes and on the insulation film prior to forming said electro-conductive film, and heat-treating them.
50. A method of manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming MISFETs on the principal surface of a semiconductor substrate and then an insulation film for covering the MISFETs; (b) etching the insulation film in order to have openings on the source/drain regions of the MISFETs; (c) depositing an electro-conductive film to fill the openings, forming wires; and (d) depositing a metal film containing titanium, tungsten or cobalt as principal ingredient on the bottom of the contact holes and on the insulation film, and annealing the metal film in an atmosphere of silicon hydride gas prior to forming said electro-conductive film.
51. A method of manufacturing a semiconductor integrated circuit device according to claim 47, wherein the unreacted titanium, tungsten or cobalt is selectively removed by etching after the step of heat-treating the metal film.
52. A method of manufacturing a semiconductor integrated circuit device according to claim 47, wherein the electro-conductive film is a laminate film of titanium nitride and tungsten, or a three-layered laminate film of titanium, titanium nitride and tungsten.
53. A method of manufacturing a semiconductor integrated circuit device according to claim 48, wherein the unreacted titanium, tungsten or cobalt is selectively removed by etching after the step of heat-treating the metal film.
54. A method of manufacturing a semiconductor integrated circuit device according to claim 48, wherein the electro-conductive film is a laminate film of titanium nitride and tungsten, or a three-layered laminate film of, titanium, titanium nitride and tungsten.
55. A method of manufacturing a semiconductor integrated circuit device according to claim 49, wherein the unreacted titanium, tungsten or cobalt is selectively removed by etching after the step of heat-treating the metal film.
56. A method of manufacturing a semiconductor integrated circuit device according to claim 49, wherein the electro-conductive film is a laminate film of titanium nitride and tungsten, or a three-layered laminate film of titanium, titanium nitride and tungsten.
57. A method of manufacturing a semiconductor integrated circuit device according to claim 50, wherein the unreacted titanium, tungsten or cobalt is selectively removed by etching after the step of heat-treating the metal film.
58. A method of manufacturing a semiconductor integrated circuit device according to claim 50, wherein the electro-conductive film is a laminate film of titanium nitride and tungsten, or a three-layered laminate film of titanium, titanium nitride and tungsten.
59. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming MISFETs on the principal surface of a semiconductor substrate; (b) depositing a metal film containing titanium, tungsten or cobalt as principal ingredient to a film thickness between 10 and 20 nm in areas covering at least the source/drain regions of the MISFETs; (c) heat-treating the metal film to form a silicide film in areas contacting the silicon; (d) selectively removing the unreacted titanium, tungsten or cobalt by etching; (e) forming an insulation film for covering the MISFETS; (f) etching the insulation film on the source/drain regions of the MISFETs so as to produce contact holes in the insulation film; and (g) depositing an electro-conductive film to fill the contact holes, and forming wires.
60. A method of manufacturing a semiconductor integrated circuit device according to claim 59, wherein the electro-conductive film is a laminate film of titanium nitride and tungsten or a three-layered laminate film of titanium, titanium nitride and tungsten.
61. A method of a semiconductor integrated circuit device having a first MISFET for a memory cell and a second MISFET for a peripheral circuit, comprising the steps of: (a) forming a first MISFET at a first portion of a semiconductor substrate and a second MISFET at a second portion of said semiconductor substrate; (b) forming a first insulating film covering said first and second MISFETs; (c) performing a first etching to said first insulating film in order to form a first contact hole to expose one of source and drain regions of said first MISFET; (d) depositing a polycrystal silicon film in said first contact hole and removing said polycrystal silicon film on said first insulating film so as to form a first plug electrode in said first contact hole; (e) forming a second insulating film over said first insulating film and said first plug electrode; (f) performing a second etching to said second insulating film in order to form a second contact hole to expose the surface of said first plug electrode, and performing said second etching to said second and first insulating films in order to form a third contact hole to expose one of source and drain regions of said second MISFET; (g) depositing a first metal film in said second and third contact holes in order to fill said second and third contact holes, and etching said first metal film on said second insulating film and leaving said first metal film into said second and third contact holes so as to form a second plug electrode in said second contact hole and a third plug electrode in said third contact hole; and (h) depositing a second metal film over said second insulating film and patterning said second metal film in order to form a bit line conductor electrically connected to said second plug electrode and a wiring conductor electrically connected to said third plug electrode.